Unlike in Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs), non-volatile memory devices can retain stored information when not powered. An example of a non-volatile memory device is an EEPROM device. EEPROM devices are electrically programmed in a similar manner to Erasable Programmable Read-Only Memories (EPROM), but unlike EPROMs, erasing can be performed selectively per unit cell using an electrical system.
Conventionally, EEPROM devices included can be included in mobile goods such as mobile phones and personal digital assistants (PDAs) together with a display unit. For example, an EEPROM device may be installed in an LDI (i.e., a device that connects a display unit to a driving circuit unit), and store intrinsic information (e.g., item name or product specification) about a mobile item in order to supply product information to the display unit. Here, an organic electroluminescence device or a liquid crystal display may be employed as the display unit.
The display unit may be formed on a glass substrate and be driven by a low voltage or a voltage in an intermediate voltage band of less than 15V. However, a general EEPROM device typically requires a high voltage of 20V and even higher for programming and erasing. Therefore, it may be necessary to change the design of the EEPROM device integrated in the LDI so that the EEPROM device can be driven by a low voltage or an intermediate voltage.
To achieve this change, a technique has been suggested to further install an access transistor and an erase transistor so that an EEPROM device can be programmed (written/read) and erased by a low voltage and an intermediate voltage. Thus, in a conventional EEPROM device, a predetermined voltage may be directly applied to a gate, a source, a drain and a body to perform programming and erasing, but a high voltage should be applied to the body when erasing. Meanwhile, an access transistor and an erase transistor, driven by an intermediate voltage and a low voltage, respectively are electrically connected to the EEPROM device, and thus programming (writing/reading) and erasing can be performed without directly supplying a high voltage to the EEPROM device. Accordingly, the EEPROM can be driven by the voltage(s) used in the LDI.
The foregoing conventional non-volatile memory device will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a non-volatile memory device integrated in a conventional LDI, and FIG. 2 is a sectional view of the non-volatile memory device of FIG. 1 taken along a line II-II′ of FIG. 1.
Referring to FIGS. 1 and 2, a first n-well 15a and a second n-well 15b are formed within a semiconductor substrate 10. The first n-well 15a is a region where an EEPROM device (E2RPOM) and an access transistor AT will be formed. The second n-well 15b is a region where an erase transistor ET will be formed. The second n-well 15b, where the erase transistor ET will be formed, should be supplied with an intermediate voltage (of about 12V) when operating the erase transistor ET. Therefore, in order to exclude an electrical influence upon the first n-well 15a by the voltage applied to the second n-well 15b, the first and second n-wells 15a and 15b should be spaced apart from each other by a predetermined distance S. If the first n-well 15a and the second n-well 15b are not separated or are adjacently disposed, punchthrough may occur in the access transistor AT due to an influence of the voltage on the second n-well 15b when the intermediate voltage is supplied to a body (i.e., the second n-well 15b) of the erase transistor ET to erase data. Accordingly, the first n-well 15a and the second n-well 15b may be spaced apart from each other by the distance S (e.g., 10˜15 μm, so as not to be significantly affected by mutual voltages.
In order to form an NMOS-type access transistor AT in a predetermined portion of the first n-well 15a, a pocket p-well 20 is formed. Device isolating layers 25 are formed in the first n-well 15a including the pocket p-well 20 and the second n-well 15b to define an active region where an access transistor region, an erase transistor region and a body contact region are substantially formed.
A floating gate 35 is formed on the first n-well 15a. The floating gate 35 extends over the first n-well 15a and the second n-well 15b to be a gate (hereinafter referred to as access gate 35a) of the access transistor AT and a gate (hereinafter referred to as erase gate 35b) of the erase transistor ET. In other words, the access gate 35a and the erase gate 35b are disposed to one side of the floating gate 35. A lower gate consisting of the floating gate 35, the access gate 35a and the erase gate 35b is electrically floated. Also, a gate insulating layer 30 is interposed between the floating gate 35 and the substrate 10. A control gate 45 is formed on an upper surface of the floating gate 35, and an inter-gate insulating layer 40 is interposed between the floating gate 35 and the control gate 45.
N-type source/drain regions 50 are formed in the active region on both sides of the access gate 35a, and p-type source/drain regions 60 are formed in the active region on both sides of the erase gate 35b. The n-type source/drain regions 50 and the p-type source/drain regions 60 are illustrated as being disposed under the access gate 35a and the erase gate 35b in FIG. 2, but, substantially, are mostly hidden by being disposed in the active region on both sides of the access gate 30b and the erase gate 30c. Therefore, they are denoted by dotted lines.
When forming the n-type source/drain regions 50, a body contact region B1 of the first n-well 15a and a body contact region B2 of the second n-well 15b are formed. Additionally, a body contact region B3 of the pocket p-well 20 is formed when forming the p-type source/drain regions 60. Here, a reference numeral C1 denotes a contact of the control gate, C2 denotes a contact of the access transistor AT, and C3 denotes a contact of the erase gate 35b. 
Because the sizes of mobile devices are continually being reduced, an area occupied by the LDI and an area of a non-volatile memory device integrated in the LDI installed in the mobile devices must be decreased. However, the size of the EEPROM (E2PROM) is directly related to its storage capacity and a width of the access transistor AT and a width of the erase transistor ET are formed with minimum feature sizes. Therefore, it may be difficult to shrink the size of the EEPROM without reducing storage capacity. Moreover, since the first and second n-wells 15a and 15b are spaced apart from each other by a predetermined distance S, which is the minimum distance required, to prevent punchthrough, it is difficult to decrease the distance S. Consequently, it may be difficult to decrease the area of the non-volatile memory device to meet a need for higher integration of the LDI.